Low dielectric constant (“low-k”) dielectric materials (or interlayer dielectric layers, “ILD's”) play an important role in the future development of advanced integrated circuit manufacturing, enabling the use of copper interconnects in sub-0.18 micron fabrication processes. Low-k ILD's are used in integrated circuit manufacturing to insulate copper interconnects from their surroundings, ensuring less cross talk between interconnections. Cross talk is a common problem in integrated circuit manufacturing, as it causes malfunction in the circuit. Cross talk becomes even more pronounced as the size of the integrated circuit continues to shrink. The dielectric constant of conventional interlayer materials used in integrated circuit manufacturing ordinarily resides in the >3.0 range. However, with the continued increase in the density of inputs/outputs on a single chip, the cross talk concerns increase.
Thus, low-K ILD's having dielectric constants below about 2.5 are an important aspect of the design of integrated circuits to maximize the efficiency of ever more compact integrated circuits. One such material is known as Black Diamond, and is commercially available from Applied Materials.
Announcements within the industry indicating the trend to 0.09 micron, and even 0.065 micron, chip fabrication processes using low-k ILD's have been reported. Progress in that regard has been hampered to date, however, as chipmakers struggle with achieving acceptable package level reliability.
Conventional electronic packaging materials, such as low coefficient of thermal expansion (“CTE”), high modulus, epoxy-based molding compounds, encapsulants, die attach adhesive materials and underfill sealant materials appear to be incapable of providing the necessary protection against package stresses to prevent damage to the low-k ILD's. The low-k ILD's, being fragile in nature, are generally weaker and more brittle than conventional ILD materials, such as silicon oxides, silicon nitrides, fluorinated silicon glass, and the like, and as a result lead to fracture and cracks during thermal excursions due to induced stresses. The fracture and cracking translate into delamination when coupled with such conventional electronic packaging materials. (See FIG. 4). Significant research and development resources have been expended in an attempt to resolve the ILD cracking issues through packaging process adjustments and material property optimizations. Little progress has been reported to date, however, at reducing the internal package stresses that lead to the low-k ILD cracking failures.
It would be desirable therefore to provide an electronic packaging material suitable for advanced applications, such as underfill sealants materials, encapsulant materials, die attach adhesive materials and molding compounds, that are compatible for use with low-k ILD's and reduce the internal package stresses that lead to ILD cracking failures. In addition, it would be desirable to provide electronic packages assembled with such ILD's and provide methods of manufacturing such electronic packages that provide enhanced physical properties.